1. Field of the Invention
The present invention relates to a data reception device and related method, and more particularly, to a data latch circuit with a phase selector, and a related method.
2. Description of the Prior Art
It is a large challenge for systems to keep each clock of a chip synchronous in some interface systems or larger chips. The chips on hand usually include digital circuits and analog circuits wherein the digital circuits occupy almost 80% of the chip area. Therefore, clock driving strength outputted from the digital circuits and capacitor effect caused from circuit layouts are estimated by circuit designers when a timing problem appears in the whole integrated circuit. Finally, clock phase errors are solved through the digital circuits by analyzing and estimating the delays between the clock signal utilized in the analog circuits and the clock signal outputted from the original clock source. Another timing problem is when a system has two clock generators with asynchronous clock signals, as timing violations can occur in the flip-flops or the data latch elements.
Two successive D type flip-flops are used as data latch elements in general circuit designs in the prior art to prevent inconsistent clock signals. Repeat sampling is processed on the inputted data to ensure accuracy of data sampling. As shown in FIG. 1, a data latch circuit 100 in the prior art includes three flip-flops 102, 104, and 106 connected in series. The flip-flop 102 used for receiving an input data Din is triggered by a first clock signal CLK1. The following two flip-flops 104 and 106 are triggered by a second clock signal CLK2. A data output end of the last flip-flop 106 is used for latching an output data Dout. However, the data latch circuit 100 will have data error due to insufficient setup times and hold times. As shown in FIG. 2, a data D2 obtained by the flip-flop 104 is not guaranteed due to a data D1 being transformed when the flip-flop 104 samples the data D1 to get the data D2 during the period when the flip-flop 102 is sampling the input data Din. Hence, the accuracy of the output data Dout generated later is influenced. In other words, although the accuracy of sampling data is improved by utilizing two successive data latch elements (the flip-flops 104 and 106) in the data latch circuit 100, sampling errors result from improper phase relation between the first clock signal CLK1 and the second clock signal CLK2.